On-chip learning of a domain-wall-synapse-crossbar-array-based convolutional neural network

Abstract Domain-wall-synapse-based crossbar arrays have been shown to be very efficient, in terms of speed and energy consumption, while implementing fully connected neural network algorithms for simple data-classification tasks, both inference on-chip-learning modes. But more complex realistic convolutional networks (CNN) need trained through such arrays. In this paper, we carry out device–circuit–system co-design co-simulation on-chip learning a CNN using domain-wall-synapse-based array. For purpose, use combination micromagnetic-physics-based synapse-device modeling, SPICE simulation crossbar-array circuit synapse devices, system-level-coding high-level language. our design, each synaptic weight the kernel is considered 15 bits; one domain-wall-synapse array dedicated five least significant bits (LSBs), two are other bits. The accelerate matrix vector multiplication operation involved forward computation CNN. weights LSB updated after on every training sample, crossbars ten samples, achieve learning. We report high classification-accuracy numbers different machine-learning data sets method. also study how classification accuracy designed affected by device-to-device variations, cycle-to-cycle bit precision weights, frequency updates.